製品概要: The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest
CPLD MAX 7000 Family 1.25K Gates 64 Macro Cells 125MHz 5V 68-Pin PLCC
■ 技術的パラメータ SeriesMAX 7000 Memory TypeEEPROM Number of Macrocells64 Maximum Operating Frequency222.2 MHz Delay Time4.5 ns Number of Programmable I/Os68 Operating Supply Voltage3.3 V Maximum Operating Temperature+ 70 C Minimum Operating Temperature0 C Package / CaseFBGA-100 Mounting StyleSMD/SMT PackagingTray Supply Voltage Max3.6 V Supply Voltage Min3 V